In conventional processor designs, protecting devices from electrostatic discharge (ESD) voltage spikes is a significant problem. For example, providing ESD protection for I/O circuits while maintaining the ability of the product to function as intended in normal operation is a challenge. The problem is particularly pronounced when the devices are being assembled into a larger package. This is because the device (chip) may be exposed to ESD events in a variety of places, but particularly during sorting, packaging, transporting, and final placement on a product circuit board. Therefore, to protect the device, ESD protection is installed for sensitive parts of the device, which limits the voltage at the sensitive area to an acceptable level for an ESD event of a given magnitude.
For instance, one method of ESD protection could employ diodes as shown in FIG. 1. A diode is either forward or reverse biased. If a diode is forward biased, it conducts; whereas, if the diode is reverse biased, it does not conduct. When a diode is forward biased, the voltage on the diode's cathode is less than the voltage on the diode's anode. The difference in voltage required to forward bias a diode is the activation voltage, which is the magnitude of the minimum voltage difference between the anode and the cathode required to forward bias a diode (where the voltage applied to the cathode is lower than the voltage applied to the anode). Since the activation voltage of a diode is usually around 0.6 volts, to forward bias a diode, the voltage on the anode must be at least 0.6 volts higher than the voltage on the cathode.
Diodes could be coupled to an input/output (I/O) pad. In such an example, the anode of a first diode is tied to the cathode of a second. A connection is made between the anode of the first diode and the I/O pad. The anode of the second diode is tied to ground, and the cathode of the first diode is tied to the system high voltage (Vdd). When the voltage difference between the I/O pad and ground exceeds the activation voltage of the second diode, the second diode becomes forward biased and creates a conducting path from ground to the I/O pad.
Connecting the I/O pad to ground through the second diode protects the input coupled to the I/O pad by preventing the magnitude of the voltage difference between ground and the I/O pad from exceeding the activation voltage of the second diode. When the voltage difference between the I/O pad and Vdd exceeds the activation voltage of the first diode, the first diode becomes forward biased and creates a conducting path from Vdd to the I/O pad. Connecting the I/O pad to Vdd through the first diode protects the input coupled to the I/O pad by preventing the magnitude of the voltage difference between Vdd and the I/O pad from exceeding the activation voltage of the first diode.
However, as the processing speeds of devices have increased, the frequency of voltage oscillations on the I/O pad has also increased. Also, as the clock frequency of a device approaches 2 GigaHertz, the capacitance effect of the ESD protection diodes becomes problematic. For example, coupling the first diode to Vdd and the second to ground creates capacitance when the diodes are reverse biased. Under ordinary circumstances, diodes laid out in series with one another can mitigate the capacitance, but placing the diodes in series does not eliminate the capacitance because the capacitance of the diodes varies non-linearly. Also, placing them in series can have a detrimental affect to the ESD robustness of the design since the I/O pad voltage will climb to a higher level before all of the diodes in the series reach their activation energy. Likewise, laying out diodes in parallel merely increases the capacitance effect. Ultimately, the excess capacitance created by the diodes limits the effective signaling speed of the I/O pad.
To compensate for ESD events, it is also known to use e-fuses directly in the path of an ESD device, where resistance values are on the order of <500Ω pre-blow and >5 kΩ post-blow. However, the large pre-blow series resistance makes their use in the discharge path problematic since the resistance in this path must be kept very low.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.